In a prior-art home VTR, in a recording system and a reproducing system there is commonly provided a so-called ACC circuit in which an amplitude of a color burst signal is detected to control a gain of a chrominance signal amplifier thereby maintaining an amplitude of the chrominance signal constant FIG. 4 shows a previously-proposed semiconductor apparatus used in this ACC circuit.
The VTR and the ACC circuit according to the prior art will be described with reference to FIGS. 1 and 2.
FIG. 1 shows an example of an arrangement of a reproducing system of a prior-art VTR.
Referring to FIG. 1, reproduced outputs from a pair of rotary magnetic heads 1A and 1B are commonly supplied through a head change-over switch 2 and an amplifier 3 to a high-pass filter 4 and a low-pass filter 5 from which there are separated an FM luminance signal Y.sub.FM and a down converted chrominance signal C.sub.L.
The FM luminance signal Y.sub.FM is supplied to a luminance signal processing circuit 7 which includes an FM-demodulator 6, and a reproduced luminance signal Y therefrom is supplied to an adder 8.
The down-converted chrominance signal C.sub.L is supplied through a chrominance signal amplifier 11 to a frequency converting circuit 12, in which it is converted to an original carrier chrominance signal C in response to an output from a local oscillator not shown The reproduced carrier chrominance signal C from the frequency converting circuit 12 is supplied to the adder 8 through a bandpass filter 13 whose center frequency is a color subcarrier frequency fsc, and the adder 8 derives a color video signal
A burst gate circuit 14 is supplied with the output of the bandpass filter 13, and the reproduced color burst signal extracted thereby is supplied to an ACC detector 15. The detected output therefrom is supplied through an ACC circuit 20 to the chrominance signal amplifier 11 of which the gain is therefore ACC-controlled.
In order to protect the chrominance signal from a flicker caused by an output level difference when the characteristics of the rotary magnetic heads 1A and 1B are not equal, the ACC circuit 20 employs capacitors 21A and 21B of the same capacitance to form time constant circuits having time constants different in field. The time constant circuits are changed-over by the switching pulse from a pulse generator 9 in synchronism with the switching operation of the rotary heads 1A and 1B.
As shown in FIG. 2, in the prior-art ACC circuit 20, the capacitors 21A and 21B are respectively connected to output terminals of differential amplifiers (comparing circuits) 22A and 22B. The differential amplifiers 22A and 22B are alternately supplied at non-inverting input terminals thereof with a detected output V.sub.15 applied to an input terminal 20i of the ACC circuit 20 from the ACC detector 15 through a change-over switch 23i at every field, and they are also commonly supplied at their inverting input terminals with a reference voltage Vr of a reference voltage source 24. The differential amplifiers 22A and 22B respectively supply the corresponding capacitors 21A and 21B with output currents corresponding to differences between the ACC detected output voltage V.sub.15 and the reference voltage Vr. The terminal voltages across the capacitors 21A and 21B are alternately supplied through buffer amplifiers (buffers) 25A and 25B and a change-over switch 23o to an output terminal 20o at every field. The switches 23i and 23o are changed in position at every field in response to the switching pulse from a control terminal 20c in a ganged-fashion.
In the conventional ACC circuit shown in FIG. 2, the two signal systems respectively including the differential amplifiers 22A and 22B are switched by the switches 23i and 23o, which provides a large-sized circuit scale and a complicated arrangement. Further, even when they are formed as an integrated circuit on the same semiconductor substrate, there is then a fear that an offset will occur between the characteristics of the two differential amplifiers.
To solve the above-noted problem, the present applicant has previously proposed, as disclosed in Japanese Utility Model Application No. 61-200570, an Acc circuit in which an output of a single comparing circuit is held by a plurality of capacitors which are switched at every field in synchronism with the change-over of rotary heads.
The previously-proposed ACC circuit will be explained with reference to FIG. 3.
FIG. 3 shows an example of an arrangement of the previously-proposed ACC circuit. In FIG. 3, like parts corresponding to those of FIG. 2 are marked with the same references.
In FIG. 3, reference numeral 20S generally designates an ACC circuit which mainly comprises a single differential amplifier 22, a pair of capacitors 21A and 21B whose one electrodes are commonly connected to the output terminal of the differential amplifier and a change-over switch 26 which alternately grounds the other electrodes of the two capacitors 21A and 21B at every field.
The previously-proposed ACC circuit 20S is operated as follows.
When one rotary head 1A (see FIG. 1) scans a magnetic tape, the change-over switch 26 is connected as shown by a dashed line. The ACC detected output from the input terminal 20i and the reference voltage Vr are level-compared by the differential amplifier 22, and a current corresponding to the level difference is supplied from the differential amplifier 22 to one capacitor 21A. Thus, its terminal voltage becomes a value corresponding to the difference between the burst signal level and the reference voltage Vr.
When the other rotary head 1B scans the magnetic tape, the switch 26 is connected as shown by a solid line, whereby the other capacitor 21B is charged up similarly as described above.
The terminal voltages across the capacitors 21A and 21B are delivered through, for example, an emitter-follower-type buffer 25 to the output terminal 20o and then supplied to the amplifier 11 (see FIG. 1). The gain of the amplifier 11 is therefore controlled such that the level of the color burst signal coincides with the reference level
According to the previously-proposed ACC circuit as described above, only the single differential amplifier is required so that the circuit scale becomes small, the arrangement is simplified and that the offset is prevented from being caused between the differential amplifiers.
When the above-mentioned, previously-proposed ACC circuit is formed on a semiconductor circuit (formed as an IC) including the capacitors 21A and 21B, it is unavoidable that the capacitors 21A and 21B are accompanied with parasitic capacitances 27A and 27B a shown by dashed lines in FIG. 3.
This is because the capacitor mounted on the semiconductor integrated circuit is generally formed as a so-called MIS (metal insulation substrate) capacitance as shown in FIG. 4.
In FIG. 4, reference numeral 31 designates a P-type silicon substrate in which an N-type epitaxial layer 32 is formed on its surface portion as an island-shape. Further, an n.sup.+ -type diffusion layer 33 is selectively formed on the surface portion of the N-type epitaxial layer 32 by the emitter diffusion-process. Through an oxide film 35 for protecting the surface of the semiconductor, large and small windows 36a nd 36b are formed on the diffusion layer 33.
A dielectric layer 37 is, for example, 500 .ANG. in thickness and is made of nitride silicon Si.sub.3 N.sub.4. This dielectric layer is deposited on the n.sup.+ -type diffusion layer 33 within the large window 36a of the oxide film 35. An Al electrode 38a is deposited on the dielectric layer 37 and an Al electrode 38b is deposited on the diffusion layer 33 within the small window 36b, whereby the diffusion layer 33 and the Al electrode 38a are opposed to each other through the dielectric layer 37, thus forming a capacitor having a capacitance of, for example, 100 pF.
A junction capacitance C.sub.j exists between the n-type island 32 communicated to the n.sup.+ -type diffusion layer 33 and the p-type silicon substrate 31 of earth potential as is conventional, and this junction capacitance C.sub.j becomes the parasitic capacitance of the capacitor which is constructed by the MIS technique. The value of the parasitic capacitance depends on constituents of the p-type silicon substrate 31 and the n-type island 32, and is generally about 10% of the capacitance of the capacitor constructed by the MIS technique.
The p-type substrate 31 and the n-type island 32 have a characteristic of a diode D.sub.j as well as the above-noted junction capacitance C.sub.j.
If the previously-proposed ACC circuit shown in FIG. 3 is formed as an IC, the parasitic capacitances 27A and 27B are produced by the above-noted junction capacitance so that the independence of the two capacitors 21A and 21B will no be kept even if the switch 26 is changed over.
When the change-over switch 26 is connected as shown by the solid line in FIG. 3, to the other capacitor 21B grounded thereby, a serially-mixed capacitance of one capacitor 21A and the parasitic capacitance 27A thereof is connected in parallel.
In like a manner, when the switch 26 is connected as shown by the dashed line, to one capacitor 21A, a serially-mixed capacitance of the other capacitor 21B and the parasitic capacitance 27B thereby is connected in
Assuming that the capacitance values of the parasitic capacitances 27A and 27B are, for example, 10% of the capacitance values of the corresponding capacitors 21A and 21B respectively as described hereinabove, then the values of the serially-mixed capacitances reach, for example, values a little larger than 9 % of the capacitance values of the capacitors 21A and 21B.
Thus, when the previously-proposed ACC circuit 20S is formed as an IC, the independence of each of the capacitors 21A and 21B is damaged so that a cross-talk occurs between the ACC control signals of each field held in the capacitors 21A and 21B. As a result, the flicker of the chrominance signal can not be eliminated completely.
If the output current from the differential amplifier 22 is supplied through the change-over switch to first electrodes of the pair of capacitors and the second electrodes of the two capacitors are grounded unlike FIG. 3, the problem of the parasitic capacitances will be solved. There are then presented problems such as the occurrence of a leak current of a switching element used to switch the current, a decrease of D.C. voltage availability (dynamic range) and the like.
In the semiconductor apparatus of FIG. 4, the dielectric layer 37 is thin in thickness and is small in electrostatic strength, whereby the electrode 38a is interconnected and the electrode 38b is led out to the outside as an MIS capacitance terminal. When the potential of the electrode 38b is lowered to the winding region, the junction diode Dj is turned ON, permitting an excess current to flow from the substrate 31 to the n-type island 32. There is then presented a problem that it becomes impossible to use the semiconductor apparatus.